The Versatile Interface Adapter
Even though the MC3 is in its core a Motorola 68xx design it can use 65xx parts. The bus and timings are the same. I initially planed on building an I/O board around the 6321 PIA but ended up trying out the feature packed 6522 VIA instead. The 6522 is actually still being manufactured by WDC! The 6522 is familiar to anyone working with the 6502 or MOS/Commodore machines. In general it's a souped up 6821 with two timers and a shift register. The 6522 consumes more address space than the 6821 but each register can be directly addressed, thus making it faster for certain tasks. It requires four address pins instead of only two but for me that's a perfect match since my I/O boards each have 4 address lines making it a 1:1 match. Connecting the 6522 to the MC3 20-pin I/O expansion bus require no extra circuitry. It's only a matter of connecting the corresponding pins together. Since there is no IRQ line on the I/O bus I will have to settle for polling the 6522. Thank you Douglas Beattie for sharing your Eagle 65xx library. The 40-pin chip is a tight fit on the small 20-pin I/O board but it worked. For now there are no connectors for the 6522 ports. Not much space left but I should be able to mount a suitable connector at the top of the board. I really like how the 6522 engineers have separated the bus pins and the I/O pins to different sides of the chip.

Inside the 6522

Above is the block diagram as seen in the G65SC22 datasheet. The 6522 has two 8-bit ports with two handshake lines each. Both ports are controlled by their corresponding data register and data direction register (just like the 6821 and many other designs based on the same concept). It also has two 16-bit timers and a shift register. Care must be taken to avoid the infamous shift register bug happening in mode 011, external clocking of the shift register. The bug occurs when the shift register clock input falls at about the same time as the Φ2 clock falls, making the shift register lose one data bit. Very strange framing errors can occur when it happens. Garth Wilson has proposed a neat solution for this that involves an external latch. Rumors has it that some variants of the 6522 does not suffer from this bug. I have a used the G65SC22 from CMD in my design that supposedly have this bug fixed. I need to set up a test to see if this is the case. In general, when dealing with the 6522 you have to assume all of them contains the bug in mode 011. The other shift register modes are unaffected as far as I know.
by gerardo pintor alarcon 2017-02-28 22:50 UTC
You can support me with an example diagram and more information.

by JOHNNY QUEST 2021-02-21 05:46 UTC
Helllo Daniel: Nice articles you've posted. I've recently decided to design a MC68B09/HD63B09 based SBC. Fairly simple design with 32KB of SRAM and 30K of UV-E/EPROM (lower 2KB address space is dedicated for I/O). I'm using the HD63B50 and an AT16V8 PLD for the decoding. The 6x09 is running at 7.3728MHz, which gives an E clock of 1.8432MHz for the HD63B50 and a baud rate of 115.2kbaud (or 28.8kbaud). I have several 6821's but also found I also had two 6522's (OEM is COMMADORE BUSINESS MACHINES) in my archive collection. Its nice to have the timers and serial interface of the 6522 and feed the 6809's NMI interrupt for system timing. I allowed a single 24-pin I/O header to provide 3 additional I/O decodes and the lower 4 address lines. Your CF card interface looks simple and clean but I have not looked into obtaining any. I plan to post the build as I go along. I've got some posts on some other "vintage" single-board computers, including the INS8073 w/ NCS NIBL BASIC interpreter from the early 80's. Its a wire-wrap build of mine from that era (I was like 19 years of age then!). If you are interested, the link is at The other SBC posts can be accessed from the links at the top of the page. Q: do you know where I can get the source code for FLEX-09, which is the 6809 version of the FLEX OS? Peace and blessings, Johnny

by DeeCee 2023-10-31 00:40 UTC
Johnny, Note that 6809 FLEX requires RAM at $C000-$DFFF. The official TSC source code (not a disassembly) is available in the FLEX-4-UniFLEX archive at: Note that the file type is TAR. The two main files are "fms" and "dos". I have modified it to support up to 10 drives instead of only 4, and to allow adding the time of file creation to directory entries.

by DeeCee 2023-10-31 00:45 UTC
I am using the 6522/VIA's shift register to implement a half-duplex SPI port, which runs at half the system clock frequency:

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