*************** * DO SINGLE STEP SSTEP JSR PCRLF STEP LDS SP RESTORE PROGRAM STACK POINTER TSX LDAA ,X LOAD CC ANDA #$EF CLEAR INTERUPT MASK BIT STAA ,X SAVE CC LDAB #$1F STPWAI DECB WAIT FOR EVENTUAL SCI XFER CMPB #$00 BEFORE TIMER INIT BNE STPWAI LDX #STOP SET INTERRUPT VECTOR STX TMOFVEC+1 LDX #$FFED RESET COUNTER VALUE STX COUNTHI LDX TIMECON CLEAR INTERRUPT BIT IN TIMER CTRL REG LDAA #$04 ENABLE TIMER OVERFLOW INTERRUPT STAA TIMECON RTI *************** * SINGLE STEP INTERRUPT ENTRY STOP STS SP SAVE PROGRAM STACK POINTER LDX #INTSEQ RESTORE INTERRUPT VECTOR STX TMOFVEC+1 LDX TIMECON CLEARS INTERRUPT BIT IN TIMER CTRL REG LDAA #$00 DISABLE TIMER INTERRUPT STAA TIMECON LDX SP EXTRACT PROGRAM STOP ADDRESS LDAB #6 ABX LDX ,X CPX #$C000 BHI STEP NO STOP IN ROM STX XTEMP LDAB XTEMP CMPB #$7F BEQ STEP NO STOP IN PAGE $7F LDX #STOPTX JSR PDATA JMP PRTREG PRINT REGS AND GO TO PROMPTMonitor 1.4.1 ($C000-$C7E8) - source - listing - s19
2015-12-03 05:48 UTC
This is a minor bug-fix release of the 1.4 monitor improving stability of the the single step function and improves stack handling and coherency in printout. This is the correct single step code. Silly me forgot to clear the interrupt mask on stack before RTI.
by Grant B 2018-02-01 22:30 UTC
Hi, I'm just looking at the Single Step code and was wondering about one instruction in particular (at least at the moment). Actually it occurs twice here it seems: LDX TIMECON ;CLEAR INTERRUPT BIT IN TIMER CTRL REG Even in page 0, isn't LDX a 16-bit read? Aren't you going to read $08 and $09? Any issues there? Did you need to burn an extra cycle or something? Thanks, GB
by Daniel 2018-02-04 00:31 UTC
Hi Grant! Thank you for spotting this. Good find! You are absolutely right. The register is 8-bit wide. The timing for this routine is the result of some extended trial and error. I remember in SSTEP I needed an extra cycle so doing an LDX was an easy way. Why it appears in other places is probably a silly cut-and-past mistake :)
by Grant B 2018-02-05 03:29 UTC
OK cool. I'm going to try a few things and I will start with your implementation first since it works. Then I might try and do a variation where the free-running counter is not modified but instead the output compare is used and generates an interrupt on adding a fixed value and then on a match triggering an output compare. I haven't thought it out any further though so I don't know if that generates an interrupt by itself or if I need to tie the OC pin to NMI or something. My target system uses overflow so I want to mess with that as little as possible in the Monitor. We'll see.